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Design Verification Engineer - remote possible

Bridgewater, NJ · Information Technology
  • Duration: 9-12 month Contract, with probable extension. (Contract to perm may be possible)
  • The Start date is March (preferred) or early April
  • Rate -  in the $60 to $95/hr range - DOE
  • Local candidates are preferred to have access to the client office (post-Covid) but fully remote is OK.
  • Great project for a Large, well-known parent company but work in remotely or in the small, growing design center
This position involves:
  • Create or leverage existing test benches to develop top-level test bench using Verilog, SV, and UVM for a Communications Receiver ASIC
  • Work with system architecture team and analog engineers to implement verification requirements in the test environment and test cases
  • Create or update drivers, monitors, agents, probes, and test patterns
  • Create or update behavioral models for analog components
  • Create and maintain test plans and use spreadsheets or other methods to track results
  • Develop test cases, run RTL and gate simulations based on system scenarios, and debug failures
  • Set up and run nightly regressions for RTL simulations and gate level simulations
  • Report and coordinate all aspects of the verification tasks in all phases of the project
Who Will Be a Great Fit?  
  • 7+ years of experience in digital verification.
  • Strong knowledge and experience using System Verilog and UVM
  • Ability to integrate C models, Matlab models, create scripts using Python, Tcl, or Perl
  • Knowledge of Cadence tools for verification
  • Willingness and ability to learn and contribute quickly
  • Ability to work in collaboration with others
  • Strongly desired - knowledge of digital signal processing, communications, C/C++, Matlab

As recruiters, we are skilled in our field and understand how to match an opportunity with the individual. If you choose to send us your resume, be advised we will not share it with any employer without your permission. 

Brian Hughes
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