Jobs at Great Bay Staffing Group

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Staff Physical Design Engineer

Santa Clara, CA · Information Technology · 210000
  • Salary in the $180 - 210,000 range
  • Comprehensive Benefit and Retirement Programs etc.
  • Relocation Paid
  • Great company with a ton of IP, growth opportunity.

This an exciting opportunity to work for an excellent worldwide business in its North American expansion. Working from the NA headquarters, you'll have the opportunity to be a key contributor working with some great individuals. The Physical Design Engineer will see the product design through from start to finish. The Staff Physical Design Engineer will work closely with customer, frontend, and integration teams to ensure successful tape-outs. Top-level and block-level experience is required. This is a hands-on technical position with opportunities to work on a variety of challenging designs.

Key Duties:

  • Participate in technical and scheduled discussions with ASIC clients and design teams on a regular basis.
  • Chip/Block Level Floorplanning and pin assignment
  • Pre-layout STA to ascertain feasibility, timing constraint validation and feedback to customers and design teams
  • Review top-level/block-level clock specifications for completeness and feasibility
  • Handle all the Physical design tasks (Placement, Timing Optimization, Clock Tree Synthesis, Routing)
  • Perform sign-off tasks (RC Extraction, Static Timing Analysis, IR drop analysis and Physical Verification)

Who Will Be a Great Fit?  
  • BSEE, MSEE preferred.
  • Strong experience in ASIC Physical Design; Experience in an SoC product development organization with tape-outs at 28nm/16nm design nodes
  • Hands-on Experience with implementation EDA tools like ICC2/Innovus
  • Experience in both Flat and Hierarchical layouts.
  • Strong problem-solving skills and the ability to analyze and resolve physical design issues related to the library, timing constraints or CAD tools is required.
  • Experience with power analysis and IR-drop tools (primepower/Redhawk) and Static Timing Analysis (Primetime)
  • Experience with Physical Verification and fix PV errors in layout
  • Expert handling of Verilog HDL based Netlists, Physical design libraries, and Scripting (Perl/Tcl/Python) is required
  • Good understanding of ASIC frontend design.
  • Team player with good interpersonal and communication skills
  • experience in ASIC/SOC services company desired
  • Small company/organization experience desired
  • International or Japanese experience is a plus

As recruiters, we are skilled in our field and understand how to match an opportunity with the individual. If you choose to send us your resume, be advised we will not share it with any employer without your permission. 

If this isn't the right position for you, please share it with someone who might be interested. In the meantime, please look at our website – we have other openings that may suit your needs!

Thank you,

Brian Hughes
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